CAN Bus Bit Timing Calculator
Generate register-ready bit timing parameters for STM32, ESP32, and NXP S32K. Select your MCU, enter the APB clock, choose the target baud rate, and get copy-paste C code.
Register Code Snippet
CAN_InitTypeDef hcan; hcan.Prescaler = 4; hcan.TimeSeg1 = CAN_BS1_16TQ; hcan.TimeSeg2 = CAN_BS2_4TQ; hcan.SyncJumpWidth = CAN_SJW_4TQ;
CAN Bus Bit Timing Explained
CAN bus timing is divided into discrete units called Time Quanta (TQ). Each bit is composed of multiple TQ segments: the Sync segment (always 1 TQ), the propagation and phase segment 1 (TSEG1/BS1), and the phase segment 2 (TSEG2/BS2).
Baud Rate Formula
Baud Rate = f_clk / (Prescaler × (1 + TSEG1 + TSEG2))
The total TQ per bit = 1 (sync) + TSEG1 + TSEG2. The calculator searches over valid prescaler and TQ combinations to find the setting closest to your target baud rate.
Sample Point
Sample Point = (1 + TSEG1) / (1 + TSEG1 + TSEG2) × 100%
The sample point is where the CAN controller reads the bus state within each bit. CiA 601 recommends 75–87.5%. A sample point too early may sample before the signal settles (propagation delay); too late leaves insufficient time for resynchronization.
MCU-Specific Clock Notes
| MCU | CAN Clock Source | Typical Value |
|---|---|---|
| STM32F4 | APB1 (PCLK1) | 42 MHz (at 168MHz sysclk) |
| STM32H7 | APB1 or FDCAN kernel clock | 80–100 MHz |
| ESP32 | APB clock (80MHz) | 80 MHz |
| NXP S32K | FlexCAN source clock | 40–80 MHz |
Design Example: STM32F4 at 500 kbps
- APB1 clock = 42 MHz (168 MHz sysclk, AHB/2)
- Target baud rate = 500 kbps
- TQ per bit needed for an 80% sample point at a reasonable TQ count → TSEG1 = 12, TSEG2 = 3 (16 TQ total, sample point = 13/16 = 81.25%)
- Prescaler = 42e6 / (500e3 × 16) = 5.25 → not an integer, so drop to 14 TQ: TSEG1 = 11, TSEG2 = 2 → Prescaler = 42e6 / (500e3 × 14) = 6.0 ✓
- SJW = min(4, TSEG2) = 2
- Actual baud rate = 42e6 / (6 × 14) = 500.0 kbps (0% error)
This is exactly the kind of search-for-an-integer-prescaler problem that makes CAN timing tedious to hand-calculate — the calculator above automates this search and also flags the resulting baud rate error against the ±1.5% CAN spec limit.
Common Mistakes in CAN Bit Timing Configuration
- Assuming APB1 = sysclk. On STM32, the CAN peripheral clock is almost never the same as the core clock — it depends on the AHB/APB prescaler tree configured in CubeMX or RCC registers. Reading this wrong is the single most common cause of a node that transmits fine locally but can't sync with the rest of the bus.
- Matching baud rate but not sample point across nodes from different vendors. Two ECUs can both report "500 kbps" correctly while using different TSEG1/TSEG2 splits (different sample points). This works fine on the bench with two nodes and starts throwing bus-off errors once a third node or longer wiring harness is added — the mismatched sample points reduce noise margin.
- Ignoring oscillator tolerance stack-up. The ±1.5% CAN baud rate budget is shared across all nodes. A node using an internal RC oscillator (rather than a crystal) can easily consume most of that budget alone — CAN nodes intended for production should use crystal or crystal-disciplined clock sources, not the internal RC oscillator some MCUs default to.
- Setting SJW to the maximum "for safety." A larger SJW does improve resynchronization range, but it also eats into TSEG2 and can push the sample point later than intended. SJW = min(4, TSEG2) is a reasonable default, not a hard rule — for high oscillator tolerance situations, dedicate more explicit budget to it rather than maximizing blindly.
Frequently Asked Questions
What clock frequency should I use for STM32F4 CAN?
STM32F4 CAN is clocked from APB1. At the standard 168MHz system clock (AHB/2 = 84MHz, APB1/2 = 42MHz), use 42MHz. Check your RCC configuration in CubeMX or your startup code to confirm the actual APB1 frequency.
What is the recommended sample point?
CiA 601 recommends 75–87.5%. Most automotive designs use 80%. The calculator automatically targets this range. If you need a specific sample point, adjust TSEG1 and TSEG2 manually using the formula above.
What is SJW?
SJW (Synchronization Jump Width) is the maximum number of TQ by which the bit timing may be shortened or lengthened during resynchronization to stay in sync with a transmitting node. Larger SJW improves noise immunity but reduces the maximum allowable oscillator tolerance. Values of 1–4 TQ are typical.
My baud rate error is more than 1% — is that a problem?
CAN specification allows up to ±1.5% baud rate error for the bus as a whole. If two nodes each have 1% error in opposite directions, the total difference is 2% — potentially causing bit errors. Try a different clock frequency or use a PLL configuration that gives a more compatible CAN clock.