MOSFET Gate Driver Resistor Calculator

Gate Resistor Design Explained

The gate resistor controls how fast the MOSFET turns on and off. A lower Rg means faster switching and lower switching losses, but higher dV/dt and dI/dt which can cause EMI, ringing, and voltage overshoot. Choosing the right Rg is a tradeoff between switching losses and EMI/overshoot.

Rise Time Formula

Rg = tr / (2.2 × Ciss)

This is the standard RC 10%–90% rise time formula. The factor 2.2 comes from ln(9) ≈ 2.197 for an RC charging circuit. Ciss is the input capacitance from the MOSFET datasheet (Cgs + Cgd with drain shorted to source). Note: the actual gate charge behavior is non-linear due to the Miller plateau, so treat this as a first-order estimate.

Gate Drive Power Loss

P_gate = Ciss × Vdrv² × f

This is the energy dissipated charging and discharging the gate capacitance each switching cycle. It is independent of Rg — Rg only determines where the loss occurs (in the resistor vs. the driver IC). A 1000pF gate, 12V drive, 500kHz switching dissipates approximately 72mW.

Where to Find Ciss in the Datasheet

Look for the "Capacitance vs. Drain-to-Source Voltage" curve in the MOSFET datasheet. Use the Ciss value at your actual operating Vds — capacitance drops significantly as Vds increases. Many designers use the Ciss at Vds = 0V (worst case) for conservative estimates.

Separate Turn-On and Turn-Off Resistors

In half-bridge and full-bridge designs, it is common to use separate gate resistors for turn-on (Rg_on) and turn-off (Rg_off) using a diode. A higher Rg_on slows the turn-on (reducing dI/dt and current ringing), while a lower Rg_off allows fast turn-off (reducing conduction losses in the body diode).

Design Example: 650V SiC MOSFET, 12V Drive, 100kHz

• Ciss from datasheet at Vds = 0V → 1,200 pF
• Target rise time tr = 30 ns
• Rg = 30e-9 / (2.2 × 1200e-12) = 11.4 Ω → round to nearest E12 value, 12 Ω
• P_gate = 1200e-12 × 12² × 100e3 = 17.3 mW (split between Rg and driver output stage)
• Peak gate current Ig = Vdrv / Rg = 12 / 12 = 1.0 A — check this against the driver IC's peak source/sink current rating

Note the jump from a 4.7–10Ω value typical for silicon MOSFETs to 12Ω here — SiC devices have higher transconductance and are more prone to gate ringing from package/PCB parasitic inductance, so designs often land slightly higher than the first-order formula suggests. Start here, then check for ringing on the bench.

Common Mistakes in Gate Resistor Selection

• Trusting the calculated Rg without scoping the gate waveform. The RC formula ignores the Miller plateau and PCB/package parasitic inductance. Always verify Vgs on the bench with a scope — ringing above the driver's absolute max rating will kill the part, sometimes not immediately.
• Using the same Rg for turn-on and turn-off in a half-bridge. Fast turn-off is usually desirable to minimize body-diode reverse recovery conduction time, while turn-on often needs to be slower to control dI/dt-induced ringing at the switch node. One resistor value is a compromise, not an optimum.
• Placing the gate resistor far from the MOSFET gate pin. Trace inductance between the resistor and the gate adds to the effective loop inductance and can undo the damping the resistor was supposed to provide. Keep the gate-source loop as short and tight as physically possible.
• Sizing Rg for the fastest possible switching to minimize losses. Faster edges reduce switching loss but increase EMI and voltage overshoot on the drain. If the design has EMC certification requirements, a slightly larger Rg than the "optimal" loss number is often the practical choice.

Frequently Asked Questions

What is a typical gate resistor value?
Values typically range from 2Ω to 33Ω. Low-voltage MOSFETs (<100V) often use 4.7–10Ω. High-voltage IGBTs and SiC MOSFETs often need 10–47Ω to prevent oscillation due to higher parasitic inductances in the package.

Can I use 0Ω for the gate resistor?
Rarely. Without any resistance, the gate current is limited only by the driver output impedance and PCB parasitic inductance, which can cause high-frequency oscillation and damage the gate driver. Most designs have at least 1–2Ω in series with the gate.