PCB Thermal Via Calculator
Estimate the equivalent thermal resistance and junction temperature drop for a copper-plated thermal via array placed under a power IC pad.
Via & Board Specifications
mm
μm
mm
pcs
W
Recommended Design Values:
- Drill diameter: 0.3 mm (most effective)
- Plating thickness: 25 μm (1 mil standard)
- Via array: 3×3 (9 vias) or 4×4 (16 vias)
- Drill diameter: 0.3 mm (most effective)
- Plating thickness: 25 μm (1 mil standard)
- Via array: 3×3 (9 vias) or 4×4 (16 vias)
Thermal Design Results
Single Via Thermal Resistance (Rθ,via)189.95K/W
Array Equivalent Thermal Resistance (Rθ,total)21.11K/W
Temperature Rise Through Vias (ΔT)42.21°C
Thermal Via Cross-Section Model
PCB Thermal Via Heat Conduction
Power semiconductors (LDO regulators, buck ICs, power MOSFETs) generate significant heat through internal losses. Standard FR-4 epoxy substrate has very poor thermal conductivity (~0.25 W/m·K) and cannot spread heat effectively. Copper-plated thermal vias (390 W/m·K) placed under the IC's exposed thermal pad conduct heat down to inner layers or the bottom copper plane acting as a heatsink.
Thermal Resistance Calculation and Temperature Margin
Thermal vias behave like parallel resistors: the larger the via cross-section (larger drill, thicker plating) and the greater the number of vias, the lower the total thermal resistance Rθ,total.
- Why 0.3 mm drill size? Larger vias (>0.5 mm) risk solder wicking during reflow assembly, where solder flows into the via barrel and starves the pad joint. 0.3 mm balances thermal efficiency with solder-wicking prevention.
- Plating thickness margin: Standard PCB through-hole plating is 25 μm (1 mil). Military-grade or harsh-environment boards often specify 35 μm or heavy copper plating to further reduce thermal resistance.